1. Field of the Invention
The present invention relates to a resin-encapsulated semiconductor device, and more particularly, to a so-called flat package semiconductor device having a flat lead so that a bottom surface of a semiconductor package and a bottom surface of the lead are flush with each other.
2. Description of the Related Art
Various electronic devices, including portable devices, are becoming thinner, smaller, and lighter. Semiconductor packages to be mounted on the electronic devices are also required to be thinner and smaller. Thinning and downsizing of the semiconductor package cannot be achieved by a related-art gullwing type semiconductor package. It is thus effective to employ a so-called flat package, which has a flat lead so that a bottom surface of the semiconductor package and a bottom surface of the lead are flush with each other.
In the flat package, a lead for connection to a circuit board is exposed from a rear surface of the package (surface to be mounted on the circuit board). Further, an island that is a portion for mounting a semiconductor chip thereon is generally formed of a lead frame, a plated layer, or the like, and the island is exposed from the rear surface of the package in some cases and not in other cases. In addition, in some semiconductor packages, no island is formed but a semiconductor chip is directly mounted on an encapsulation resin. When the flat package is mounted on a circuit board with solder, a bottom surface of an outer lead and a pattern of the circuit board are bonded to each other with solder.
A method of manufacturing a related-art flat package is described with reference to the drawings.
FIGS. 10A to 10G are cross-sectional views illustrating the method of manufacturing the related-art semiconductor package in the order of steps. Referring to FIG. 10A, a photo resist 2 is applied and patterned on a conductive base plate 3, and a plated layer 1 is formed in an opening of the photo resist 2 to form an electrode of the semiconductor package. The plated layer 1 is formed of three layers in many cases. A gold or silver plated layer is formed on the conductive base plate 3, a nickel or copper plated layer is formed thereon, and further a gold or silver plated layer is formed thereon. Referring to FIG. 10B, the photo resist 2 is removed. Referring to FIG. 10C, a semiconductor chip 7 is die-bonded on an island 36 formed of the plated layer 1, and a wire 8 is electrically connected to an outer lead 30 similarly formed of the plated layer 1. Referring to FIG. 10D, an encapsulation resin layer 9 is formed in order to protect the semiconductor chip 7, the wire 8, and the like. Referring to FIG. 10E, the conductive base plate 3 is removed. FIG. 10F illustrates dicing with a dicing blade 10 for singulating the semiconductor package. In dicing, the outer lead 30 formed of the plated layer 1 is cut. FIG. 10G illustrates the final cross section of the semiconductor package. An end surface 31 of the outer lead 30 is exposed.
The dicing step involves cutting the outer lead 30 formed of the plated layer 1, and hence nickel or copper is exposed from the end surface 31 as a cutting surface. FIG. 11 is a cross-sectional view illustrating a state in which the semiconductor package manufactured by the related-art manufacturing method is bonded on a circuit board 13 with solder 11. Because a gold plated layer or a silver plated layer is exposed from a bottom surface 32 of the outer lead 30, solder wettability is good and a satisfactory bonded state with solder is obtained (see, for example, Japanese Patent Application Laid-open No. 2002-9196).
Further, a technology of forming a material with good solderability on a cutting surface of an outer lead in a related-art gullwing type semiconductor package is disclosed in Japanese Patent Application Laid-open Nos. Hei 8-213540 and Hei 7-030043.
As described above, more and more packaged semiconductor devices have employed the flat type due to the thinning, downsizing, and lightening of electronic devices.
In the structure illustrated in FIG. 11, however, the main material of the plated layer 1 such as nickel or copper is exposed on the end surface 31 of the outer lead 30, and hence solder wettability is poor and it is difficult to bond the semiconductor package with solder. Accordingly, as illustrated in FIG. 11, a good solder fillet cannot be obtained from the end surface 31 and hence a sufficient bonding area cannot be obtained in bonding with the circuit board, thus resulting in a problem of low bonding strength. Further, automatic visual inspection using image inspection, which is performed after the semiconductor package is bonded on the circuit board with solder, determines a pass/fail of a connection state between the outer lead 30 and solder 11 by observing the shape of the fillet. However, because the solder fillet is not bonded on the end surface 31 of the outer lead 30, a pass/fail of the connection state cannot be determined simply by observing the fillet. Thus, there is another problem in that automatic visual inspection cannot be applied to the flat package.